Profile of GaN Die Edge

11:22 AM

Wafer dicing is the process of separating a finished semiconductor wafer into individual dies. While it appears straightforward compared to the complexity of front-end fabrication, it is a process step where significant yield loss can occur if not tightly controlled. For standard silicon devices, diamond blade dicing is well established, but power semiconductors introduce a set of material and geometry challenges that make dicing considerably more demanding. Gallium nitride (GaN) and silicon carbide (SiC) — the two dominant wide bandgap materials for power devices — are both substantially harder and more brittle than silicon. This hardness makes blade dicing slow and prone to generating microcracks and chipping at the die edge.

Power devices are particularly susceptible to edge defects because of their high internal electric field. A chip or crack at the die perimeter can initiate premature breakdown at voltages well below the device’s rated specification, directly reducing blocking voltage and long-term reliability. Characterising the edge profile of a singulated die — its chipping depth, sidewall angle, and surface condition — is a critical quality control step that directly predicts field reliability. This is precisely where lineWLI adds value: measuring the full edge profile of a GaN or SiC die in a single shot, at production speed, without the vibration sensitivity that makes conventional scanning interferometry impractical on the dicing line.

Here’s an overview picture of a GaN MOSFET. The profile measurement in this picture is at the indicated position going into the plane. One pixel of the full resolution picture corresponds to 1.8 µm:

The side profile reveals a few interesting features from the singulation process. The active side of the edge profile is facing towards the right. There are two cuts: one smaller cut through the active region of the device that penetrates about 150 µm into the device. Then a second cut from the backside that fully separates the dies.

The feature at 690 µm is about 26µm away from the wafer edge. This matches the lateral distance is the visible picture between the wafer edge and gray / gold boundary. What’s remarkable is that there appears to be an undercut that’s not visible from the top. Further investigation shows that this undercut is real and not an artifact of the measurement device.

Line profile of the sawed edge

There are small dips visible in the slopes of the backside cut. Measuring along the edge shows that these dips are present in the device along the edge and not a spurious measurement: